1. Field of the Invention
The present invention relates to apparatus and methods for modifying stresses in semiconductor devices. In particular, the present invention relates to modifying isolation structure configurations, such as trench depth and isolation materials used, to either induce or reduce tensile and/or compressive stresses on an active area of MOS semiconductor devices.
2. State of the Art
Semiconductor integrated circuits are formed by chemically and physically forming circuit components in and on a semiconductor substrate. These circuit components are generally conductive (e.g., for conductor and resistor fabrication) and may be of different conductivity types (e.g., for transistor and diode fabrication). Thus, when forming such circuit components, it is essential that they are electrically isolated from one another, wherein electrical communication between the isolated circuit components is achieved through discrete electrical traces.
Various techniques have been developed for electrically isolating integrated circuit components formed in the semiconductor substrate. One such technique is known as trench isolation. The trench isolation technique involves forming a channel or trench in the semiconductor substrate, usually by etching techniques well known in the art. The trench is formed to surround the circuit components to be isolated and filled with a dielectric material, thereby electrically isolating the circuit components.
FIGS. 22 and 23 illustrate in side cross-sectional view and in top plan view, respectively, components of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). As shown in FIG. 22, a source region 202 and a drain region 204 are implanted in a semiconductor substrate 206. The source region 202 and the drain region 204 may be implanted with either a p-type material, such as boron, to form a pMOS (p-channel Metal Oxide Semiconductor) transistor or an n-type material, usually phosphorous and/or arsenic, to form an nMOS (n-channel Metal Oxide Semiconductor) transistor.
A gate structure 208 spans a region of the semiconductor substrate 206 between the source region 202 and the drain region 204. An exemplary gate structure 208 comprises a conductive material 212 electrically isolated with dielectric spacers 214 and 214′adjacent the source region 202 and the drain region 204, a lower dielectric layer 216, and a cap layer 218.
The source region 202 and the drain region 204 are isolated with an isolation structure 222 (i.e., a dielectric-filled trench) extending into the semiconductor substrate 206, preferably beyond the depth of the source region 202 and the drain region 204, as shown in FIG. 22. The isolation structure 222 surrounds the source region 202 and the drain region 204, as shown in FIG. 23, to form an island or active area 224. The material which form the gate structure 208 extends beyond the active area 224 to other semiconductor device components (not shown).
It has been reported in literature that stresses on an active area can significantly effect the performance of MOS devices. Hamada in “A New Aspect of Mechanical Stress Effects in Scaled MOS Device”, IEEE Transactions on Electron Devices, vol. 38 (1991), pp. 895-900 illustrated that stresses of the order of 100 MPa can affect performance by a few percent. In the reported experiments, well-controlled uniaxial stresses were applied on MOS devices by using a 4-point bending technique. The stresses were applied both parallel and perpendicular to the channel current direction and for both nMOS and pMOS devices. The results showed that for nMOS devices, tensile stress in both directions improves performance, while compressive stress degrades performance. These effects have been found to be more significant for long channel nMOS devices. For pMOS devices, tensile stress perpendicular to the channel current direction improves performance, but tensile stress parallel to the channel current direction degrades performance, and vice versa for compressive stress.
Such degradation in performance is particularly a problem for MOS devices in flip-chip packaging configurations. FIG. 24 illustrates a cross-sectional view of such a packaging configuration. With flip-chip packaging configurations, a semiconductor die 232 is electrically attached to a carrier substrate 234, such as a printed circuit board, with the active surface 236 of the semiconductor die 232 facing the carrier substrate 234. The electrical attachment of the semiconductor die active surface 236 to the carrier substrate 234 is generally achieved by refluxing solder balls 238 between the semiconductor die active surface 236 and the carrier substrate 234 to form an electrical connection between electrical traces on or in the semiconductor die 232 (not shown) and electrical traces on the carrier substrate 234 (not shown). Once electrical attachment of the semiconductor die 232 to the carrier substrate 234 is complete, an underfill material 242 is disposed between the semiconductor die 232 and the carrier substrate 234. The resulting structure is then heated to cure the underfill material 242. However, when the resulting structure is cooled down to room temperature from the underfill cure temperature, a bending curvature develops because the carrier substrate 234 contracts more than the semiconductor die 232 (i.e., due to the thermal expansion mismatch between the carrier substrate 234 and the semiconductor die 232), as shown in FIG. 25. Such bending causes biaxial compressive stresses (illustrated by arrows 248 in FIG. 25) on MOS transistors 246 (shown schematically as rectangles in FIGS. 24 and 25) within the semiconductor die 232.
As previously discussed, these biaxial stresses will degrade nMOS device performance. However, these biaxial stresses will have less of an effect on the performance of a pMOS device due to the cancellation effects of the two perpendicular stress components (i.e., the decrease in performance due to compressive stress perpendicular to the channel current direction is offset by the increase in performance due to the compressive stress parallel to the channel current direction).
Therefore, it would be advantageous to develop a technique to effectively induce or reduce tensile and/or compressive stresses on the active area of a MOS device to improve the operating performance thereof, while utilizing commercially-available, widely-practiced semiconductor device fabrication techniques.